(1) Field of the Invention
The present invention relates to a clock synchronization of a data transmission system. More particularly, it relates to a clock synchronizing circuit of a data transmission system that can synchronize a clock of the transmitting station to a clock of the receiving station using an elastic buffer in case that there are phase deviations in the clocks of the two systems when transmitting multi-channel data between two data transmission systems distant from each other, using transmission lines different from one another in length between a plurality of sub-systems.
(2) Description of the Prior Art
Referring to FIG. 1, a conventional data transmission system comprises a transmitting station A that transmits data synchronized to an outgoing clock CLKA and a receiving station B receiving data synchronized to an incoming clock CLKB.
In such a data transmission system, the transmitting station A synchronizes outgoing data D1A to D1N to the clock CLKA and serial-transmits the data through each line driver 11A to 11N. The receiving station B then receives the data D1 to DN through each line receiver 13A to 13N, and a data processing block 15 reads incoming data D2A to D2N synchronized to the incoming clock CLKB.
In this conventional data transmission system, the receiving station cannot stably read the data synchronized at the outgoing clock on the basis of the incoming clock where there are the phase differences between the outgoing and incoming clocks. Particularly, since the clock's timing margin is small in high speed data transmission, it cannot ensure that the data synchronized at the transmitting clock is stably read out at the receiving clock.
A clock synchronizing circuit using an elastic buffer disclosed in U.S. Pat. No. 5,293,409 to Mr. Anthony Doornenbal performs simple serial data transmission irrelevant to the frame of transmitted data. The process of reading out the write data may cause undesirable violation of set up time due to the phase deviations of clocks.